FDE Tools & Documentation
A compiled list of required tools & software to work on a FDE project and maybe some tips & tricks or solutions to problems.
To work with the FDE board, we mainly need two things:
Synopsys DC compiler
Highly recommended to use an Intel x86 environment to run the DC virtual machine
Running the VM on a AMD processor might cause problems (no guarantee)
Also untested on Apple Silicon ARM CPUs (the VM performance would be terrible trying to emulate x86 architecture)
FDE workflow (import, map, pack, place, route, etc.)
The original FDE software is x86 Windows based
Modern version of FDE (UFDE+) is cross-platform compatible
Windows
MacOS (AARCH tested)
Linux (might has bugs?)
FDE-CLI (coming soon...)
FDE Tools
As mentioned above,
Original FDE tools (windows) & DC compiler VM
If you experience problems with the modern FDE tools, you can consider using the original FDE tools from 2019 or 2021.
FDE Workflow
UFDE+ (Import, map, pack, place, route, generate bitstream, & program)
Typescript & React frontend
Rust backend (FDE tools via FFI)
Cross-platform
Rabbit (GUI, virtual components)
C++
QT Framework
Windows, MacOS
FDE-CLI (CLI for debugging & interacting with FDE board with more advanced features)
Rust
SMIMS driver implemented in Rust
Cross-platform
Constraints
There are actually two types of IO ports on the FDE board: VeriComm & GPIO (general purpose IO)
VeriComm ports is what the SMIMS engine uses as input and outport ports for its SMIMS API. UFDE's constraints mapping & Rabbit's virtual components all depend on VeriComm ports because those are the only ports that the SMIMS engine can write and read to. SMIMS cannot write or read from other ports, such as GPIO.
VeriComm ports are also separated into two categories: input port and output ports. There roles are obvious, but keep in mind that it does not support inout ports. A port and only be strictly an input port or an output port.
Here is a chart of the SMIMS VeriComm input & output ports:
clk
P77
input 0
P151
output 0
P7
input 1
P148
output 1
P6
input 2
P150
output 2
P5
input 3
P152
output 3
P4
input 4
P160
output 4
P9
input 5
P161
output 5
P8
input 6
P162
output 6
P16
input 7
P163
output 7
P15
input 8
P164
output 8
P11
input 9
P165
output 9
P10
input 10
P166
output 10
P20
input 11
P169
output 11
P18
input 12
P173
output 12
P17
input 13
P174
output 13
P22
input 14
P175
output 14
P21
input 15
P191
output 15
P23
input 16
P120
output 16
P44
input 17
P116
output 17
P45
input 18
P115
output 18
P46
input 19
P114
output 19
P43
input 20
P113
output 20
P40
input 21
P112
output 21
P41
input 22
P111
output 22
P42
input 23
P108
output 23
P33
input 24
P102
output 24
P34
input 25
P101
output 25
P35
input 26
P100
output 26
P36
input 27
P97
output 27
P30
input 28
P96
output 28
P31
input 29
P95
output 29
P24
input 30
P89
output 30
P27
input 31
P88
output 31
P29
input 32
P87
output 32
P110
input 33
P86
output 33
P109
input 34
P81
output 34
P99
input 35
P75
output 35
P98
input 36
P74
output 36
P94
input 37
P70
output 37
P93
input 38
P69
output 38
P84
input 39
P68
output 39
P83
input 40
P64
output 40
P82
input 41
P62
output 41
P73
input 42
P61
output 42
P71
input 43
P58
output 43
P63
input 44
P57
output 44
P60
input 45
P49
output 45
P59
input 46
P47
output 46
P56
input 47
P48
output 47
P55
input 48
P192
output 48
P167
input 49
P193
output 49
P168
input 50
P199
output 50
P176
input 51
P200
output 51
P187
input 52
P201
output 52
P189
input 53
P202
output 53
P194
For more detailed documentation of both VeriComm & GPIO ports, refer to excel spreadsheet attached below:
Customizing your constraints file
The constraints file can be automatically generated by UFDE+, but you can also modify the generated constraints file by changing the port name or adding more ports depending on your needs as long as the file follows the XML syntax. The format should be quite straightforward so I will leave it to you to figure out how to create your own constraints file (hint: you only need to add, modify, or delete the <port ...> element & its name & position attributes).
The name attribute MUST match a port from your top module (it should match exactly and case sensitive too)
The position attribute also MUST match a physical port from the VeriComm documentation
The position attribute determines two things:
Input or output
The physical pin on the FPGA
Note: the position attribute can also be a GPIO pin if you wish to explore the unknown
Clocks
The FDE board actually has two onboard clocks:
A virtual clock generated by the SMIMS engine (P77)
A internal 30MHz clock (P185)
By default, UFDE+ only supports P77 in the constraints config and generation. But if you wish to use the internal clock, you can modify the position of the "clk" port in your constraints file to P185.
NOTE: Using the 30MHz clock to drive the FPGA, you will have to manage cross-clock domain data sharing because the SMIMS engine will be running at a different frequency than the internal clock, the engine is not in sync with the FPGA when writing to & sampling from the input and output pins (it would be a magnitude of times slower). You might have to consider using an asynchronous FIFO.
Common problems
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